(1) Field of the Invention
The present invention relates to the manufacture of ultra large scale integrated (ULSI) circuit chips in general, and in particular, to forming interconnects in a semiconductor substrate by using an improved dual damascene process.
(2) Description of the Related Art
Damascene is an old known art of inlaying, that is, inserting metal into incisions made in stone, wood or metal. The damascene process used in today's semiconductor manufacturing is a derivative of the same, except for the precision and accuracy with which the process has been developed and is being practiced. The damascene process lends itself very well to the manufacturing of very and ultra scale integrated (VLSI and ULSI) circuits where myriad interconnections are made between passive and active devices within a semiconductor substrate, as well as between a multitude of wiring layers that constitute the circuits on the substrate. Damascene is a process which simplifies the forming of interconnections in a semiconductor substrate.
In a single damascene process, incisions, or grooves, are formed in an insulating layer and filled with metal to form conductive lines. Dual damascene takes the process one step further in that, in addition to forming the grooves of a single damascene, the conductive hole openings are also formed in the insulating layer. The resulting composite structure of grooves and holes are filled with metal. The process is repeated as many times as required to form the multi-level interconnections between metal lines and the holes formed in between. Contact holes are formed directly over the substrate where the metal in the hole contacts the surface of the substrate, while the via holes are formed between metal layers.
In contrast, conventionally, the metal layers and the interconnecting layers are formed separately, and serially. First, a first blanket metal is deposited on a first insulating layer and electrical lines are formed by subtractive etching of the metal through a first mask. A second insulating layer is formed over the first metallized layer, and the second insulating layer is patterned with holes using a second mask. The holes are then filled with metal, thus forming metal columns, or plugs, contacting the first metal layer. A second blanket-metal layer is formed over the second insulating layer containing the columnar plugs which now connect the upper second metal layer with the lower first metal layer. The second metal layer is next patterned with another mask to form a set of new electrical lines, and the process is repeated as many times as it is needed to fabricate a semiconductor substrate.
In the standard dual damascene process an insulating layer, (20), shown in FIG. 1a, is coated with a resist material, (30), which is exposed to a first mask with the image pattern of a hole opening (35') for either a contact or via hole, and the pattern is anisotropically etched, (35), in the upper half (20b) of the insulating layer. The hole depth in the insulating layer can be controlled by timed-etch. That is, the etch is stopped after a predetermined period of time. However, timed-etch is not always reliable. In order to have a better control on the depth of the hole, an etch-stop layer is also be used, as is well known in the art. Etch-stop layer is usually a thin conformal material such as silicon nitride (Si.sub.3 N.sub.4, SiN), silicon oxynitride (SiO.sub.x N.sub.y), or titanium nitride (TiN) which have high selectivity to the etchant. Thus, hole opening (35) in layer (20) stops at etch-stop layer (25) shown in FIG. 1a. The etchant is then modified to etch the hole pattern through the etch-stop layer and stop at the insulating layer below. After etching, patterned resist material (30) is removed, insulating layer (20) is coated with another resist material (40) and exposed to a second mask with image pattern of conductive lines (45') in alignment with hole openings (35). In anisotropically etching the openings for the conductive line in the upper half of the insulating material, the hole openings already present in the upper half are simultaneously etched in the lower half (20a) of the insulating material. After the etching is complete, both the hole openings and conductive line openings are filled with metal (50), and any excess material on the surface of the substrate is removed by chemical mechanical polishing.
In another approach for the dual damascene process, the conductive line openings, (45'), are etched first into the upper half of the insulating material, (20b), as shown in FIG. 2a, using an etch-stop layer (25). Resist material, (30), is next formed over the substrate, thus filling the line opening (45), and patterned with hole opening (35'), as shown in FIG. 2b. The hole pattern is then etched into the lower half (20a) of the insulating material, thus forming the dual damascene structure. Again, after the etching is complete, both the hole openings and conductive line openings are filled with metal (50), and any excess material on the surface of the substrate is removed by chemical mechanical polishing.
Other variations on the damascene interconnect process are disclosed in U.S. Pat. No. 5,589,706, U.S. Pat. No. 5,602,053, U.S. Pat. 5,614,765 in which the latter patent discloses a self-aligned dual damascene. In U.S. Pat. No. 5,422,309, Zettler, et al., teach a method for forming an interconnect. An opening is formed in an insulating layer. For producing an interconnect mask, a photoresist layer is applied, exposed and developed such that the surface of the regions to be contacted remains covered with photoresist in exposed regions, whereas the surface of the insulating layer is uncovered in the exposed regions. Using the interconnect mask as etching mask, conductive line openings are etched into the insulating layer. Oshaki, et al., in U.S. Pat. No. 5,677,243 show a method of forming a multi-layer interconnection. The method includes: forming a hole reaching the first conductive layer in the insulating layer; forming an organic layer at least filling the hole; removing a portion of the insulating layer at a portion at which the insulating layer contacts an organic layer filling the hole; removing the organic layer filling the hole to form a recessed portion continuous to the hole in the insulating layer; and forming a second conductive layer in such a manner that it fills the hole and the recessed portion.
Although standard dual damascene processes offer advantages over other conventional processes for forming interconnections, there are a number of disadvantages, such as the edges of the hole openings in the lower half of the insulating layer being poorly defined because of the two etchings and the hole edges being unprotected during the second etching. The problem is illustrated in FIG. 3a, which is a three-dimensional rendition of a portion of FIG. 1b. As can be seen there, edge (23) of hole opening (35) in the lower portion (20a) of the insulating layer (20) is irregular and nonuniform due to etching. Furthermore, adequate nitride corner selectivity during etching contact/via hole is difficult to achieve for proper hole edge profile integrity. Also, nitride thickness should be relatively thin (&lt;1500 .ANG.) to avoid stride stress and associated crack. High photoresist selectivity is required for uniformity of hole edge, and critical dimension (CD) control of the hole opening (35) as well as that of conductive line opening (45). Thus, improvements are needed in the prior art damascene processes to provide better contact/via hole profile as shown in FIG. 3b and as disclosed in the embodiments of this invention.